22#define INTERRUPT_BASE_ADDR 0xB000
23#define INTERRUPT_BASICPEND (INTERRUPT_BASE_ADDR+0x200)
24#define INTERRUPT_IRQPEND1 (INTERRUPT_BASE_ADDR+0x204)
25#define INTERRUPT_IRQPEND2 (INTERRUPT_BASE_ADDR+0x208)
26#define INTERRUPT_FIQCONTROL (INTERRUPT_BASE_ADDR+0x20C)
27#define INTERRUPT_ENABLEIRQ1 (INTERRUPT_BASE_ADDR+0x210)
28#define INTERRUPT_ENABLEIRQ2 (INTERRUPT_BASE_ADDR+0x214)
29#define INTERRUPT_ENABLEBASICIRQ (INTERRUPT_BASE_ADDR+0x218)
30#define INTERRUPT_DISABLEIRQ1 (INTERRUPT_BASE_ADDR+0x21C)
31#define INTERRUPT_DISABLEIRQ2 (INTERRUPT_BASE_ADDR+0x220)
32#define INTERRUPT_DISABLEBASICIRQ (INTERRUPT_BASE_ADDR+0x224)
33 #define IRQSYSTIMERC1 1
34 #define IRQSYSTIMERC3 3
92 for (
Size i = 0; i < 64; i++)
110 case 9:
return (basic & (1 << 11));
116 return (pend1 & (1 << vector));
118 return (pend2 & (1 << (vector-32)));
#define INTERRUPT_DISABLEIRQ1
#define INTERRUPT_DISABLEIRQ2
#define INTERRUPT_DISABLEIRQ1
#define INTERRUPT_IRQPEND1
#define INTERRUPT_ENABLEIRQ2
#define INTERRUPT_BASICPEND
#define INTERRUPT_IRQPEND2
#define INTERRUPT_DISABLEIRQ2
#define INTERRUPT_ENABLEIRQ1
void write(u32 reg, u32 data)
write to memory mapped I/O register
u32 read(u32 reg) const
read from memory mapped I/O register
virtual bool isTriggered(uint vector)
Check if an IRQ vector is set.
virtual Result disable(uint vector)
Disable an IRQ vector.
BroadcomInterrupt()
Constructor.
virtual Result clear(uint vector)
Clear an IRQ vector.
virtual Result enable(uint vector)
Enable an IRQ vector.
virtual Result nextPending(uint &irq)
Retrieve the next pending interrupt (IRQ).
Interrupt controller interface.
unsigned int u32
Unsigned 32-bit number.
unsigned int uint
Unsigned integer number.
unsigned int Size
Any sane size indicator cannot go negative.