ARMGenericInterrupt.h

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/*
 * Copyright (C) 2019 Niek Linnenbank
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
#ifndef __LIBARCH_ARM_ARMGENERICINTERRUPT_H
#define __LIBARCH_ARM_ARMGENERICINTERRUPT_H
 
#include <IntController.h>
#include "ARMIO.h"
 
class ARMGenericInterrupt : public IntController
{
  private:
 
    static const Size NumberOfSoftwareInterrupts = 16;
 
    enum DistRegisters
    {
        GICD_CTRL       = 0x0000,
        GICD_TYPER      = 0x0004,
        GICD_GROUPR     = 0x0080,
        GICD_ISENABLER  = 0x0100,
        GICD_ICENABLER  = 0x0180,
        GICD_ICPENDR    = 0x0280,
        GICD_ISACTIVER  = 0x0300,
        GICD_ICACTIVER  = 0x0380,
        GICD_IPRIORITYR = 0x0400,
        GICD_ITARGETSR  = 0x0800,
        GICD_ICFGR      = 0x0C00,
        GICD_SGIR       = 0x0F00,
        GICD_CPENDSGIR  = 0x0F10,
        GICD_ID2        = 0x0FE8
    };
 
    enum DistCtrlFlags
    {
        DistCtrlGroup0 = (1 << 0),
        DistCtrlGroup1 = (1 << 1)
    };
 
    enum DistTypeFlags
    {
        DistTypeIrqsMask = (0xf)
    };
 
    enum CpuRegisters
    {
        GICC_CTRL      = 0x0000,
        GICC_PMR       = 0x0004,
        GICC_IAR       = 0x000C,
        GICC_EOIR      = 0x0010,
        GICC_IDR       = 0x00FC,
        GICC_DIR       = 0x1000
    };
 
    enum CpuCtrlFlags
    {
        CpuCtrlGroup0 = (1 << 0),
        CpuCtrlGroup1 = (1 << 1)
    };
 
    enum CpuIrqAckFlags
    {
        CpuIrqAckMask  = (0x3ff),
    };
 
  public:
 
    ARMGenericInterrupt(Address distRegisterBase,
                        Address cpuRegisterBase);
 
    Result initialize(bool performReset = true);
 
    virtual Result send(const uint targetCoreId, const uint irq);
 
    virtual Result enable(uint irq);
 
    virtual Result disable(uint irq);
 
    virtual Result clear(uint irq);
 
    virtual Result nextPending(uint & irq);
 
    virtual bool isTriggered(uint irq);
 
  private:
 
    Size numRegisters(Size bits) const;
 
    bool isSoftwareInterrupt(const uint irq) const;
 
  private:
 
    ARMIO m_dist;
 
    ARMIO m_cpu;
 
    Size m_numIrqs;
 
    u32 m_savedIrqAck;
};
 
#endif /* __LIBARCH_ARM_ARMGENERICINTERRUPT_H */