#include <Types.h>
#include <Macros.h>

Data Structures
struct	CPUState
	Contains all the CPU registers. More...

Namespaces
namespace	ARM64Control
	ARM64 System Control Coprocessor (CP15).

namespace	SystemControlFlags
	System Control flags.

Macros
#define	PA_RANGE(r) ((r)&0xF)

#define	TGRAN4(r) (((r)>>28)&0xF)

#define	tlb_invalidate(virt)

#define	isb() { asm volatile ("isb" ::: "memory"); }
	Instruction Synchronisation Barrier (ARMv7 and above)

#define	dsb(type) { asm volatile ("dsb "#type ::: "memory"); }
	Data Memory Barrier.

#define	dmb() { asm volatile ("dmb sy" ::: "memory"); }
	Data Memory Barrier.

#define	enable_interrupt() { asm volatile ("msr daifclr, #2") ; }

#define	disable_interrupt() { asm volatile ("msr daifset, #2") ; }

#define	timestamp() 0
	Reads the CPU's timestamp counter.

#define	cpu_reboot()
	Reboot the system.

#define	cpu_shutdown()
	Shutdown the machine via ACPI.

#define	idle() asm volatile ("wfi")
	Puts the CPU in a lower power consuming state.

#define	exception_code(esr) (((esr)>>26)&0x3f)

Enumerations
enum	ARM64Control::Register { ARM64Control::MainID = 0 , ARM64Control::CoreID , ARM64Control::SystemControl , ARM64Control::AuxControl , ARM64Control::DomainControl , ARM64Control::TranslationTable0 , ARM64Control::TranslationTable1 , ARM64Control::TranslationTableCtrl , ARM64Control::CacheClear , ARM64Control::DataCacheClean , ARM64Control::FlushPrefetchBuffer , ARM64Control::InstructionCacheClear , ARM64Control::InstructionTLBClear , ARM64Control::DataTLBClear , ARM64Control::UnifiedTLBClear , ARM64Control::UserProcID , ARM64Control::InstructionFaultAddress , ARM64Control::InstructionFaultStatus , ARM64Control::DataFaultAddress , ARM64Control::DataFaultStatus , ARM64Control::SystemFrequency , ARM64Control::PhysicalTimerValue , ARM64Control::PhysicalTimerControl , ARM64Control::PhysicalTimerCount , ARM64Control::MemoryModelFeature , ARM64Control::MemoryAttrIndirection , ARM64Control::VectorBaseAddress , ARM64Control::DAIF }
	System Control Registers. More...

enum	ARM64Control::AuxControlFlags { ARM64Control::DisablePageColoring = (1 << 6) , ARM64Control::SMPBit = (1 << 6) }
	Aux Control flags. More...

enum	ARM64Control::DomainControlFlags { ARM64Control::DomainClient = 1 , ARM64Control::DomainManager = 3 }
	Domain Control flags. More...

enum	{ SystemControlFlags::MMUEnabled = (1 << 0) , SystemControlFlags::AlignCheckEnabled = (1 << 1) , SystemControlFlags::Stage1Cache = (1 << 2) , SystemControlFlags::SA = (1 << 2) , SystemControlFlags::SA0 = (1 << 3) , SystemControlFlags::InstrCache = (1 << 12) , SystemControlFlags::WXN = (1 << 19) , SystemControlFlags::E0E = (1 << 24) , SystemControlFlags::EE = (1 << 25) }

Functions
u64	ARM64Control::read (Register reg)
	Read a register from the CP15.

void	ARM64Control::write (Register reg, u64 value)
	Write register to the CP15.

void	ARM64Control::set (AuxControlFlags flags)
	Set auxillary flags in CP15.

void	ARM64Control::set (DomainControlFlags flags)
	Set domain control flags in CP15.

struct CPUState	ALIGN (8) CPUState
	Contains all the CPU registers.

Variables
enum ARM64Control::Register	ARM64Control::ALIGN

u64	x0

u64	x1

u64	x2

u64	x3

u64	x4

u64	x5

u64	x6

u64	x7

u64	x8

u64	x9

u64	x10

u64	x11

u64	x12

u64	x13

u64	x14

u64	x15

u64	x16

u64	x17

u64	x18

u64	fp

u64	lr

u64	sp

u64	esr

u64	far

u64	cpsr

u64	pc

Macro Definition Documentation

◆ cpu_reboot

#define cpu_reboot ( )

Reboot the system.

Definition at line 199 of file ARM64Control.h.

◆ cpu_shutdown

#define cpu_shutdown ( )

Shutdown the machine via ACPI.

Note: We do not have ACPI yet. Shutdown now has a bit naive implementation.

See also: http://forum.osdev.org/viewtopic.php?t=16990

Definition at line 207 of file ARM64Control.h.

◆ disable_interrupt

#define disable_interrupt ( ) { asm volatile ("msr daifset, #2") ; }

Definition at line 187 of file ARM64Control.h.

◆ dmb

#define dmb ( ) { asm volatile ("dmb sy" ::: "memory"); }

Data Memory Barrier.

Ensures that all memory transactions are complete when the next instruction runs. If the next instruction is not a memory instruction, it is allowed to run out of order. The DMB provides slightly looser memory barrier than DSB on ARM.

Definition at line 184 of file ARM64Control.h.

◆ dsb

#define dsb ( type ) { asm volatile ("dsb "#type ::: "memory"); }

Data Memory Barrier.

Ensures that all memory transactions are complete when the next instruction runs. If the next instruction is not a memory instruction, it is allowed to run out of order. The DMB provides slightly looser memory barrier than DSB on ARM.

Definition at line 173 of file ARM64Control.h.

◆ enable_interrupt

#define enable_interrupt ( ) { asm volatile ("msr daifclr, #2") ; }

Definition at line 186 of file ARM64Control.h.

◆ exception_code

#define exception_code ( esr ) (((esr)>>26)&0x3f)

Definition at line 245 of file ARM64Control.h.

◆ idle

#define idle ( ) asm volatile ("wfi")

Puts the CPU in a lower power consuming state.

Definition at line 212 of file ARM64Control.h.

◆ isb

#define isb ( ) { asm volatile ("isb" ::: "memory"); }

Instruction Synchronisation Barrier (ARMv7 and above)

Definition at line 163 of file ARM64Control.h.

◆ PA_RANGE

#define PA_RANGE ( r ) ((r)&0xF)

Definition at line 149 of file ARM64Control.h.

◆ TGRAN4

#define TGRAN4 ( r ) (((r)>>28)&0xF)

Definition at line 150 of file ARM64Control.h.

◆ timestamp

#define timestamp ( ) 0

Reads the CPU's timestamp counter.

Returns: 64-bit integer.

Definition at line 194 of file ARM64Control.h.

◆ tlb_invalidate

#define tlb_invalidate ( virt )

Value:

({ \
    asm volatile ("dsb ishst\n"\
                  "tlbi vaae1is, %0\n" \
                  "dsb ish\n" \
                  "isb" : : "r" (virt>>12UL) );\
})