ARM64Control.h

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/*
 * Copyright (C) 2025 Ivan Tan
 * Copyright (C) 2015 Niek Linnenbank
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
#ifndef __ARM64_CONTROL_H
#define __ARM64_CONTROL_H
 
#include <Types.h>
#include <Macros.h>
 
namespace ARM64Control
{
    enum Register
    {
        MainID = 0,
        CoreID,
        SystemControl,  //checked
        AuxControl,
        DomainControl,
        TranslationTable0, //checked
        TranslationTable1, //checked
        TranslationTableCtrl,//checked
        CacheClear,
        DataCacheClean,
        FlushPrefetchBuffer,
        InstructionCacheClear,
        InstructionTLBClear,
        DataTLBClear,
        UnifiedTLBClear,
        UserProcID,
        InstructionFaultAddress,
        InstructionFaultStatus,
        DataFaultAddress,
        DataFaultStatus,
        SystemFrequency,
        PhysicalTimerValue,
        PhysicalTimerControl,
        PhysicalTimerCount,
        //aarch64 new registers
        MemoryModelFeature,
        MemoryAttrIndirection,
        VectorBaseAddress,
        DAIF,
    };
 
 
    enum AuxControlFlags
    {
        DisablePageColoring = (1 << 6),
        SMPBit              = (1 << 6)
    };
 
    enum DomainControlFlags
    {
        DomainClient  = 1,
        DomainManager = 3
    };
 
    u64 read(Register reg);
 
    void write(Register reg, u64 value);
 
    void set(AuxControlFlags flags);
 
    void set(DomainControlFlags flags);
};
 
/* Macros for registers
 *
 */
 
//AArch64 Memory Model Feature Register 0
//https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0
#define PA_RANGE(r) ((r)&0xF)       //Physical Address range supported.
#define TGRAN4(r)   (((r)>>28)&0xF) //Indicates support for 4KB memory translation granule size.
 
#define tlb_invalidate(virt) \
({ \
    asm volatile ("dsb ishst\n"\
                  "tlbi vaae1is, %0\n" \
                  "dsb ish\n" \
                  "isb" : : "r" (virt>>12UL) );\
})
 
#define isb() { asm volatile ("isb" ::: "memory"); }
 
#define dsb(type) { asm volatile ("dsb "#type ::: "memory"); }
 
//FIXME: sy isn't appropriate for all scenarioes
#define dmb()  { asm volatile ("dmb sy" ::: "memory"); }
 
#define enable_interrupt() { asm volatile ("msr daifclr, #2") ; }
#define disable_interrupt() { asm volatile ("msr daifset, #2") ; }
 
#define timestamp() 0
 
#define cpu_reboot()
 
#define cpu_shutdown()
 
#define idle() \
    asm volatile ("wfi")
 
namespace SystemControlFlags {
    enum {
        MMUEnabled          = (1 << 0),
        AlignCheckEnabled   = (1 << 1),
        Stage1Cache         = (1 << 2),
        SA                  = (1 << 2),  // SP Alignment check enable
        SA0                 = (1 << 3),  // SP Alignment check enable for EL0
        InstrCache          = (1 << 12),
        WXN                 = (1 << 19), // Write permission implies XN (Execute-never).
        E0E                 = (1 << 24), // Endianness of data accesses at EL0.
        EE                  = (1 << 25), //Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime.
    };
};
 
typedef struct CPUState
{
    u64 x0, x1, x2, x3, x4, x5;
    u64 x6, x7, x8, x9, x10, x11;
    u64 x12, x13, x14, x15, x16;
    u64 x17, x18, fp, lr, sp; //sp_el0
    u64 esr, far, cpsr, pc;
}
ALIGN(8) CPUState;
 
#define exception_code(esr) (((esr)>>26)&0x3f)
 
#endif /* __ARM64_CONTROL_H */