ARMCore.h

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/*
 * Copyright (C) 2015 Niek Linnenbank
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
#ifndef __ARM_CORE_H
#define __ARM_CORE_H
 
#include <FreeNOS/Constant.h>
#include <Types.h>
#include <Macros.h>
#include "ARMControl.h"
 
#define IRQ(vector) (vector)
 
#define mrc(coproc, opcode1, opcode2, reg, subReg) \
({ \
    ulong r; \
    asm volatile("mrc " QUOTE(coproc) ", " QUOTE(opcode1) ", %0, " QUOTE(reg) ", " QUOTE(subReg) ", " QUOTE(opcode2) "\n" : "=r"(r) :: "memory"); \
    r; \
})
 
#define mcr(coproc, opcode1, opcode2, reg, subReg, value) \
({ \
    u32 val = (value); \
    asm volatile("mcr " QUOTE(coproc) ", " QUOTE(opcode1) ", %0, " QUOTE(reg) ", " QUOTE(subReg) ", " QUOTE(opcode2) "\n" : : "r"(val) : "memory"); \
})
 
#define mrrc(coproc, opcode1, CRm) \
({ \
    u64 r; \
    asm volatile("mrrc " QUOTE(coproc) ", " QUOTE(opcode1) ", %Q0, %R0, " QUOTE(CRm) "\n" : "=r"(r) :: "memory"); \
    r; \
})
 
#define mcrr(coproc, opcode1, CRm, value) \
({ \
    u64 val = (value); \
    asm volatile("mcrr " QUOTE(coproc) ", " QUOTE(opcode1) ", %Q0, %R0, " QUOTE(CRm) "\n" : : "r"(val) : "memory"); \
})
 
#define timestamp() 0
 
#define cpu_reboot()
 
#define cpu_shutdown()
 
#define idle() \
    asm volatile ("wfi")
 
#define vbar_set(addr) \
    mcr(p15, 0, 0, c12, c0, (addr))
 
#define sysctrl_read() \
    (mrc(p15, 0, 0, c1, c0))
 
#define sysctrl_write(val) \
    mcr(p15, 0, 0, c1, c0, (val))
 
#define read_core_id() \
    (mrc(p15, 0, 5, c0, c0) & 0xff)
 
#ifdef ARMV6
#define tlb_flush_all() \
({ \
    ARMControl ctrl; \
    ctrl.write(ARMControl::UnifiedTLBClear, 0); \
})
#else
inline void tlb_flush_all()
{
    asm volatile ("mcr p15, 0, %0, c8, c7, 0" :: "r"(0) : "memory");
}
#endif /* ARMV6 */
 
#define tlb_invalidate(page) \
({ \
    mcr(p15, 0, 1, c8, c7, (page)); \
})
 
inline void dmb()
{
#ifdef ARMV7
    asm volatile ("dmb" ::: "memory");
#else
    asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0));
#endif /* ARMV7 */
}
 
inline void dsb()
{
#ifdef ARMV7
    asm volatile ("dsb" ::: "memory");
#else
    asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
#endif /* ARMV7 */
}
 
inline void flushBranchPrediction()
{
    asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0) : "memory");
}
 
inline void isb()
{
#ifdef ARMV7
    asm volatile ("isb" ::: "memory");
#else
    asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory");
#endif
}
 
inline void flushPrefetchBuffer()
{
#ifdef ARMV7
    isb();
#else
    asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory");
#endif /* ARMV7 */
}
 
 
typedef struct CPUState
{
    u32 padding[4];
    u32 cpsr;
    u32 sp, lr;
    u32 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12;
    u32 pc;
}
ALIGN(4) CPUState;
 
class ARMCore
{
  public:
 
    enum Result
    {
        Success = 0,
    };
 
  public:
 
    void logException(CPUState *state) const;
 
    void logState(CPUState *state) const;
 
    void logRegister(const char *name, u32 reg, const char *text = "") const;
};
 
#endif /* __ARM_CORE_H */