ARM architecture specific code such as caching, virtual memory and exception/interrupt handling. More...

Namespaces
namespace	Arch

namespace	ARM64Control
	ARM64 System Control Coprocessor (CP15).

Data Structures
class	ARMCacheV6
	ARMv6 cache management implementation. More...

class	ARMCacheV7
	ARMv7 cache management implementation. More...

class	ARMControl
	ARM System Control Coprocessor (CP15). More...

struct	CPUState
	Contains all the CPU registers. More...

class	ARMCore
	Class representing an ARM processor core. More...

class	ARMException
	ARM exception handling functionality. More...

class	ARMFirstTable
	ARM first level page table. More...

class	ARMGenericInterrupt
	ARM Generic Interrupt Controller (GIC) version 2. More...

class	ARMIO
	Input/Output operations specific to the ARM architecture. More...

class	ARMMap
	Memory mapping for the kernel and user processes on the ARM architecture. More...

class	ARMPaging
	ARM virtual memory implementation. More...

class	ARMSecondTable
	ARM second level page table implementation. More...

class	ARMTimer
	ARM Generic Timer. More...

class	SunxiClockControl
	Allwinner Clock Control Unit (CCU) More...

class	SunxiCpuConfig
	Allwinner sunxi CPU configuration module support. More...

class	SunxiPowerManagement
	Allwinner Power, Reset and Clock Management (PRCM) module. More...

class	SunxiSystemControl
	Allwinner System Control (SYSCON) module. More...

class	ARM64Cache
	ARMv7 cache management implementation. More...

class	ARM64Exception
	ARM64 exception handling functionality. More...

class	ARM64FirstTable
	ARM64 first level page table. More...

class	ARM64IO
	Input/Output operations specific to the ARM architecture. More...

class	ARM64Map
	Memory mapping for the kernel and user processes on the ARM64 architecture. More...

class	ARM64Paging
	ARM64 virtual memory implementation. More...

class	ARM64SecondTable
	ARM64 second level page table implementation. More...

class	ARM64Timer
	ARM64 Generic Timer. More...

Macros
#define	IRQ(vector) (vector)
	Remap interrupt vector (unused for ARM)

#define	mrc(coproc, opcode1, opcode2, reg, subReg)
	Move to ARM from CoProcessor (MRC).

#define	mcr(coproc, opcode1, opcode2, reg, subReg, value)
	Move to CoProcessor from ARM (MCR).

#define	mrrc(coproc, opcode1, CRm)
	64-bit move to ARM from CoProcessor (MRC).

#define	mcrr(coproc, opcode1, CRm, value)
	64-bit move to CoProcessor from ARM (MCR).

#define	timestamp() 0
	Reads the CPU's timestamp counter.

#define	cpu_reboot()
	Reboot the system.

#define	cpu_shutdown()
	Shutdown the machine via ACPI.

#define	idle() asm volatile ("wfi")
	Puts the CPU in a lower power consuming state.

#define	vbar_set(addr) mcr(p15, 0, 0, c12, c0, (addr))
	Change Vector Base Address (VBAR)

#define	sysctrl_read() (mrc(p15, 0, 0, c1, c0))
	Read System Control register.

#define	sysctrl_write(val) mcr(p15, 0, 0, c1, c0, (val))
	Write System Control register.

#define	read_core_id() (mrc(p15, 0, 5, c0, c0) & 0xff)
	Read unique core identifier.

#define	tlb_invalidate(page)

#define	ARM_EX_VECTAB_SIZE (64)
	Size of the ARM exception vector table in bytes.

#define	ARM64_EX_VECTAB_SIZE (64)
	Size of the ARM64 exception vector table in bytes.

Functions
void	tlb_flush_all ()
	Flush the entire Translation Lookaside Buffer.

void	dmb ()
	Data Memory Barrier.

void	dsb ()
	Data Synchronisation Barrier.

void	flushBranchPrediction ()
	Flush branch prediction.

void	isb ()
	Instruction Synchronisation Barrier (ARMv7 and above)

void	flushPrefetchBuffer ()
	Flush Prefetch Buffer.

struct CPUState	ALIGN (4) CPUState
	Contains all the CPU registers.

Variables
class ARMCore	ALIGN

ARM Kernel Traps
ARM specific software interrupts. These functions are called by the user program to invoke the kernel APIs, also known as system calls. On ARM, there are no machine-specific input operand constraints to specify registers for inline assembly. Therefore, we need to use Local Register Variables syntax to guarantee that specific registers are used. See also https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables
ulong	trapKernel1 (ulong api, ulong arg1)
	Perform a kernel trap with 1 argument.

ulong	trapKernel2 (ulong api, ulong arg1, ulong arg2)
	Perform a kernel trap with 2 arguments.

ulong	trapKernel3 (ulong api, ulong arg1, ulong arg2, ulong arg3)
	Perform a kernel trap with 3 arguments.

ulong	trapKernel4 (ulong api, ulong arg1, ulong arg2, ulong arg3, ulong arg4)
	Perform a kernel trap with 4 arguments.

ulong	trapKernel5 (ulong api, ulong arg1, ulong arg2, ulong arg3, ulong arg4, ulong arg5)
	Perform a kernel trap with 5 arguments.

#define	USR_MODE 16
	ARM Program Status Register (CPSR)

#define	IRQ_MODE 18

#define	FIQ_MODE 17

#define	SVC_MODE 19

#define	ABT_MODE 23

#define	UND_MODE 27

#define	SYS_MODE 31

#define	HYP_MODE 0x1a

#define	MODE_MASK 0x1f

#define	IRQ_BIT (1 << 7)

#define	FIQ_BIT (1 << 6)

#define	ASYNC_ABORT_BIT (1 << 8)

#define	ELR .long 0xe12ef30e
	ARM Model-Specific Instructions.

#define	ERET .long 0xe160006e
	eret

#define	PAGESHIFT 12
	ARM Memory Constants.

#define	DIRSHIFT 20
	Page table bit shift.

#define	SECTIONMASK 0xfff00000
	Mask for large 1MiB section mappings.

#define	PAGESIZE 4096
	ARM uses 4K pages.

#define	PAGEDIR_MAX 4096
	Number of entries in the first-level page table.

#define	PAGEDIR_SIZE (PAGEDIR_MAX * sizeof(u32))

#define	PAGETAB_MAX 256
	Number of entries in a second-level page table.

#define	PAGETAB_SIZE (PAGETAB_MAX * sizeof(u32))

#define	PAGETAB_SPAN (PAGETAB_MAX*PAGESIZE)

#define	PAGEMASK 0xfffff000
	Mask to find the page.

#define	MEMALIGN 4
	Memory address alignment.

#define	L1_DIRSHIFT 30UL
	ARM Memory Constants.

#define	L2_DIRSHIFT 21UL

#define	L3_DIRSHIFT 12UL

#define	DIR_MASK 0x1FFUL

#define	PAGESIZE 4096
	ARM uses 4K pages.

#define	PAGEDIR_MAX 512
	Number of entries in the each level page table.

#define	PAGEDIR_SIZE (PAGEDIR_MAX * sizeof(u64))

#define	PAGETAB_MAX 256
	Number of entries in a second-level page table.

#define	PAGETAB_SIZE (PAGETAB_MAX * sizeof(u32))

#define	PAGETAB_SPAN (PAGETAB_MAX*PAGESIZE)

#define	PAGEMASK 0x3FFFFFFFFF000UL
	Mask to find the page.

#define	L1_BLOCK_MASK 0x3FFFFC0000000UL
	Mask for large 1GB block mappings.

#define	L1_BLOCK_SIZE 0x40000000UL

#define	L1_BLOCK_RANGE (L1_BLOCK_SIZE-1)

#define	L2_BLOCK_MASK 0x3FFFFFFE00000UL
	Mask for large 2MB block mappings.

#define	L2_BLOCK_SIZE 0x200000UL

#define	L2_BLOCK_RANGE (L2_BLOCK_SIZE-1)

#define	L1_IDX(va) (((va) >> L1_DIRSHIFT) & DIR_MASK)

#define	L2_IDX(va) (((va) >> L2_DIRSHIFT) & DIR_MASK)

#define	L3_IDX(va) (((va) >> L3_DIRSHIFT) & DIR_MASK)

#define	MEMALIGN 4
	Memory address alignment.

#define	PT_NONE 0

#define	PT_PAGE 0b11

#define	PT_BLOCK 0b01

#define	PT_TYPE_MASK 0b11

#define	GET_PT_TYPE(entry) ((entry) & PT_TYPE_MASK)

#define	IS_PT_PAGE_TBL(entry) (GET_PT_TYPE(entry) == PT_PAGE)

#define	IS_PT_BLOCK(entry) (GET_PT_TYPE(entry) == PT_BLOCK)

#define	PT_KERNEL (0<<6)

#define	PT_USER (1<<6)

#define	PT_RW (0<<7)

#define	PT_RO (1<<7)

#define	PT_AF (1<<10)

#define	PT_NX (1UL<<54)

#define	PT_OSH (2<<8)

#define	PT_ISH (3<<8)

#define	PT_MEM (0<<2)

#define	PT_DEV (1<<2)

#define	PT_NC (2<<2)

#define	TTBR_CNP 1

#define	contain_flags(val, flags) (((val)&(flags))==(flags))

Detailed Description

ARM architecture specific code such as caching, virtual memory and exception/interrupt handling.

Macro Definition Documentation

◆ ABT_MODE

#define ABT_MODE 23

Definition at line 50 of file ARMConstant.h.

◆ ARM64_EX_VECTAB_SIZE

#define ARM64_EX_VECTAB_SIZE (64)

Size of the ARM64 exception vector table in bytes.

Definition at line 40 of file ARM64Exception.h.

◆ ARM_EX_VECTAB_SIZE

#define ARM_EX_VECTAB_SIZE (64)

Size of the ARM exception vector table in bytes.

Definition at line 39 of file ARMException.h.

◆ ASYNC_ABORT_BIT

#define ASYNC_ABORT_BIT (1 << 8)

Definition at line 57 of file ARMConstant.h.

◆ contain_flags

#define contain_flags	(	val,
		flags
	)	(((val)&(flags))==(flags))

Definition at line 121 of file ARM64Constant.h.

◆ cpu_reboot

#define cpu_reboot ( )

Reboot the system.

Definition at line 102 of file ARMCore.h.

◆ cpu_shutdown

#define cpu_shutdown ( )

Shutdown the machine via ACPI.

Note: We do not have ACPI yet. Shutdown now has a bit naive implementation.

See also: http://forum.osdev.org/viewtopic.php?t=16990

Definition at line 110 of file ARMCore.h.

◆ DIR_MASK

#define DIR_MASK 0x1FFUL

Definition at line 48 of file ARM64Constant.h.

◆ DIRSHIFT

#define DIRSHIFT 20

Page table bit shift.

In ARM, the first-level page directory entry is selected by bits [31:20] from the virtual address, plus two 0 bytes.

See also: ARM Architecture Reference Manual, page 724.

Definition at line 94 of file ARMConstant.h.

◆ ELR

#define ELR .long 0xe12ef30e

ARM Model-Specific Instructions.

msr ELR_hyp, lr

Definition at line 69 of file ARMConstant.h.

◆ ERET

#define ERET .long 0xe160006e

eret

Definition at line 72 of file ARMConstant.h.

◆ FIQ_BIT

#define FIQ_BIT (1 << 6)

Definition at line 56 of file ARMConstant.h.

◆ FIQ_MODE

#define FIQ_MODE 17

Definition at line 48 of file ARMConstant.h.

◆ GET_PT_TYPE

#define GET_PT_TYPE ( entry ) ((entry) & PT_TYPE_MASK)

Definition at line 98 of file ARM64Constant.h.

◆ HYP_MODE

#define HYP_MODE 0x1a

Definition at line 53 of file ARMConstant.h.

◆ idle

#define idle ( ) asm volatile ("wfi")

Puts the CPU in a lower power consuming state.

Definition at line 115 of file ARMCore.h.

◆ IRQ

#define IRQ ( vector ) (vector)

Remap interrupt vector (unused for ARM)

Parameters

vector Interrupt vector number

Returns: Same interrupt vector

Definition at line 44 of file ARMCore.h.

◆ IRQ_BIT

#define IRQ_BIT (1 << 7)

Definition at line 55 of file ARMConstant.h.

◆ IRQ_MODE

#define IRQ_MODE 18

Definition at line 47 of file ARMConstant.h.

◆ IS_PT_BLOCK

#define IS_PT_BLOCK ( entry ) (GET_PT_TYPE(entry) == PT_BLOCK)

Definition at line 100 of file ARM64Constant.h.

◆ IS_PT_PAGE_TBL

#define IS_PT_PAGE_TBL ( entry ) (GET_PT_TYPE(entry) == PT_PAGE)

Definition at line 99 of file ARM64Constant.h.

◆ L1_BLOCK_MASK

#define L1_BLOCK_MASK 0x3FFFFC0000000UL

Mask for large 1GB block mappings.

Definition at line 78 of file ARM64Constant.h.

◆ L1_BLOCK_RANGE

#define L1_BLOCK_RANGE (L1_BLOCK_SIZE-1)

Definition at line 80 of file ARM64Constant.h.

◆ L1_BLOCK_SIZE

#define L1_BLOCK_SIZE 0x40000000UL

Definition at line 79 of file ARM64Constant.h.

◆ L1_DIRSHIFT

#define L1_DIRSHIFT 30UL

ARM Memory Constants.

Page table bit shift.

In ARM64, the shifts of each level vary based on granule. Assume 4K granule.

See also: https://developer.arm.com/documentation/101811/0104/Translation-granule/The-starting-level-of-address-translation

Definition at line 45 of file ARM64Constant.h.

◆ L1_IDX

#define L1_IDX ( va ) (((va) >> L1_DIRSHIFT) & DIR_MASK)

Definition at line 86 of file ARM64Constant.h.

◆ L2_BLOCK_MASK

#define L2_BLOCK_MASK 0x3FFFFFFE00000UL

Mask for large 2MB block mappings.

Definition at line 82 of file ARM64Constant.h.

◆ L2_BLOCK_RANGE

#define L2_BLOCK_RANGE (L2_BLOCK_SIZE-1)

Definition at line 84 of file ARM64Constant.h.

◆ L2_BLOCK_SIZE

#define L2_BLOCK_SIZE 0x200000UL

Definition at line 83 of file ARM64Constant.h.

◆ L2_DIRSHIFT

#define L2_DIRSHIFT 21UL

Definition at line 46 of file ARM64Constant.h.

◆ L2_IDX

#define L2_IDX ( va ) (((va) >> L2_DIRSHIFT) & DIR_MASK)

Definition at line 87 of file ARM64Constant.h.

◆ L3_DIRSHIFT

#define L3_DIRSHIFT 12UL

Definition at line 47 of file ARM64Constant.h.

◆ L3_IDX

#define L3_IDX ( va ) (((va) >> L3_DIRSHIFT) & DIR_MASK)

Definition at line 88 of file ARM64Constant.h.

◆ mcr

#define mcr	(	coproc,
		opcode1,
		opcode2,
		reg,
		subReg,
		value
	)

Value:

({ \
    u32 val = (value); \
    asm volatile("mcr " QUOTE(coproc) ", " QUOTE(opcode1) ", %0, " QUOTE(reg) ", " QUOTE(subReg) ", " QUOTE(opcode2) "\n" : : "r"(val) : "memory"); \
})

Move to CoProcessor from ARM (MCR).

Write data to CoProcessor connected to the ARM.

Definition at line 63 of file ARMCore.h.

◆ mcrr

#define mcrr	(	coproc,
		opcode1,
		CRm,
		value
	)

Value:

({ \
    u64 val = (value); \
    asm volatile("mcrr " QUOTE(coproc) ", " QUOTE(opcode1) ", %Q0, %R0, " QUOTE(CRm) "\n" : : "r"(val) : "memory"); \
})

64-bit move to CoProcessor from ARM (MCR).

Write 64-bit data to CoProcessor connected to the ARM.

Definition at line 86 of file ARMCore.h.

◆ MEMALIGN [1/2]

#define MEMALIGN 4

Memory address alignment.

Definition at line 127 of file ARMConstant.h.

◆ MEMALIGN [2/2]

#define MEMALIGN 4

Memory address alignment.

Definition at line 91 of file ARM64Constant.h.

◆ MODE_MASK

#define MODE_MASK 0x1f

Definition at line 54 of file ARMConstant.h.

◆ mrc

#define mrc	(	coproc,
		opcode1,
		opcode2,
		reg,
		subReg
	)

Value:

({ \
    ulong r; \
    asm volatile("mrc " QUOTE(coproc) ", " QUOTE(opcode1) ", %0, " QUOTE(reg) ", " QUOTE(subReg) ", " QUOTE(opcode2) "\n" : "=r"(r) :: "memory"); \
    r; \
})

Move to ARM from CoProcessor (MRC).

Read data from a CoProcessor connected to the ARM.

Definition at line 51 of file ARMCore.h.

◆ mrrc

#define mrrc	(	coproc,
		opcode1,
		CRm
	)

Value:

({ \
    u64 r; \
    asm volatile("mrrc " QUOTE(coproc) ", " QUOTE(opcode1) ", %Q0, %R0, " QUOTE(CRm) "\n" : "=r"(r) :: "memory"); \
    r; \
})

64-bit move to ARM from CoProcessor (MRC).

Read 64-bit data from a CoProcessor connected to the ARM.

Definition at line 74 of file ARMCore.h.

◆ PAGEDIR_MAX [1/2]

#define PAGEDIR_MAX 4096

Number of entries in the first-level page table.

Number of entries in the each level page table.

TTBR0 is the first-level page table for the application. TTBR1 is always 16KB, the first-level page table of the kernel/OS.

Definition at line 105 of file ARMConstant.h.

◆ PAGEDIR_MAX [2/2]

#define PAGEDIR_MAX 512

Number of entries in the each level page table.

TTBR0 is the first-level page table for the application. TTBR1 is always 16KB, the first-level page table of the kernel/OS.

Definition at line 59 of file ARM64Constant.h.

◆ PAGEDIR_SIZE [1/2]

#define PAGEDIR_SIZE (PAGEDIR_MAX * sizeof(u32))

Definition at line 106 of file ARMConstant.h.

◆ PAGEDIR_SIZE [2/2]

#define PAGEDIR_SIZE (PAGEDIR_MAX * sizeof(u64))

Definition at line 60 of file ARM64Constant.h.

◆ PAGEMASK [1/2]

#define PAGEMASK 0xfffff000

Mask to find the page.

Definition at line 121 of file ARMConstant.h.

◆ PAGEMASK [2/2]

#define PAGEMASK 0x3FFFFFFFFF000UL

Mask to find the page.

Definition at line 75 of file ARM64Constant.h.

◆ PAGESHIFT

#define PAGESHIFT 12

ARM Memory Constants.

Page entry bit shift.

Definition at line 84 of file ARMConstant.h.

◆ PAGESIZE [1/2]

#define PAGESIZE 4096

ARM uses 4K pages.

Definition at line 97 of file ARMConstant.h.

◆ PAGESIZE [2/2]

#define PAGESIZE 4096

ARM uses 4K pages.

Definition at line 51 of file ARM64Constant.h.

◆ PAGETAB_MAX [1/2]

#define PAGETAB_MAX 256

Number of entries in a second-level page table.

Second-level page tables are 1KB in size and map 1MB of virtual memory. Second-level page tables must be aligned on 1KB boundaries.

See also: ARM Architecture Reference Manual, page 734.

Definition at line 116 of file ARMConstant.h.

◆ PAGETAB_MAX [2/2]

#define PAGETAB_MAX 256

Number of entries in a second-level page table.

Second-level page tables are 1KB in size and map 1MB of virtual memory. Second-level page tables must be aligned on 1KB boundaries.

See also: ARM Architecture Reference Manual, page 734.

Definition at line 70 of file ARM64Constant.h.

◆ PAGETAB_SIZE [1/2]

#define PAGETAB_SIZE (PAGETAB_MAX * sizeof(u32))

Definition at line 117 of file ARMConstant.h.

◆ PAGETAB_SIZE [2/2]

#define PAGETAB_SIZE (PAGETAB_MAX * sizeof(u32))

Definition at line 71 of file ARM64Constant.h.

◆ PAGETAB_SPAN [1/2]

#define PAGETAB_SPAN (PAGETAB_MAX*PAGESIZE)

Definition at line 118 of file ARMConstant.h.

◆ PAGETAB_SPAN [2/2]

#define PAGETAB_SPAN (PAGETAB_MAX*PAGESIZE)

Definition at line 72 of file ARM64Constant.h.

◆ PT_AF

#define PT_AF (1<<10)

Definition at line 107 of file ARM64Constant.h.

◆ PT_BLOCK

#define PT_BLOCK 0b01

Definition at line 96 of file ARM64Constant.h.

◆ PT_DEV

#define PT_DEV (1<<2)

Definition at line 116 of file ARM64Constant.h.

◆ PT_ISH

#define PT_ISH (3<<8)

Definition at line 112 of file ARM64Constant.h.

◆ PT_KERNEL

#define PT_KERNEL (0<<6)

Definition at line 103 of file ARM64Constant.h.

◆ PT_MEM

#define PT_MEM (0<<2)

Definition at line 115 of file ARM64Constant.h.

◆ PT_NC

#define PT_NC (2<<2)

Definition at line 117 of file ARM64Constant.h.

◆ PT_NONE

#define PT_NONE 0

Definition at line 94 of file ARM64Constant.h.

◆ PT_NX

#define PT_NX (1UL<<54)

Definition at line 108 of file ARM64Constant.h.

◆ PT_OSH

#define PT_OSH (2<<8)

Definition at line 111 of file ARM64Constant.h.

◆ PT_PAGE

#define PT_PAGE 0b11

Definition at line 95 of file ARM64Constant.h.

◆ PT_RO

#define PT_RO (1<<7)

Definition at line 106 of file ARM64Constant.h.

◆ PT_RW

#define PT_RW (0<<7)

Definition at line 105 of file ARM64Constant.h.

◆ PT_TYPE_MASK

#define PT_TYPE_MASK 0b11

Definition at line 97 of file ARM64Constant.h.

◆ PT_USER

#define PT_USER (1<<6)

Definition at line 104 of file ARM64Constant.h.

◆ read_core_id

#define read_core_id ( ) (mrc(p15, 0, 5, c0, c0) & 0xff)

Read unique core identifier.

This function reads the Multi-Processor Affinity Register (MPIDR) to determine the unique identifier of the processor. Note that only the most significant affinity level 0 is used and others are ignored.

Returns: Value of affinity level 0

Definition at line 145 of file ARMCore.h.

◆ SECTIONMASK

#define SECTIONMASK 0xfff00000

Mask for large 1MiB section mappings.

Definition at line 124 of file ARMConstant.h.

◆ SVC_MODE

#define SVC_MODE 19

Definition at line 49 of file ARMConstant.h.

◆ SYS_MODE

#define SYS_MODE 31

Definition at line 52 of file ARMConstant.h.

◆ sysctrl_read

#define sysctrl_read ( ) (mrc(p15, 0, 0, c1, c0))

Read System Control register.

Definition at line 127 of file ARMCore.h.

◆ sysctrl_write

#define sysctrl_write ( val ) mcr(p15, 0, 0, c1, c0, (val))

Write System Control register.

Definition at line 133 of file ARMCore.h.

◆ timestamp

#define timestamp ( ) 0

Reads the CPU's timestamp counter.

Returns: 64-bit integer.

Definition at line 97 of file ARMCore.h.

◆ tlb_invalidate

#define tlb_invalidate ( page )

Value:

({ \
    mcr(p15, 0, 1, c8, c7, (page)); \
})

Definition at line 167 of file ARMCore.h.

◆ TTBR_CNP

#define TTBR_CNP 1

Definition at line 119 of file ARM64Constant.h.

◆ UND_MODE

#define UND_MODE 27

Definition at line 51 of file ARMConstant.h.

◆ USR_MODE

#define USR_MODE 16

ARM Program Status Register (CPSR)

Definition at line 46 of file ARMConstant.h.

◆ vbar_set

#define vbar_set ( addr ) mcr(p15, 0, 0, c12, c0, (addr))

Change Vector Base Address (VBAR)

Definition at line 121 of file ARMCore.h.

Function Documentation

◆ ALIGN()

struct CPUState ALIGN ( 4 )

Contains all the CPU registers.

References isb().

◆ dmb()

void dmb ( )

inline

Data Memory Barrier.

Ensures that all memory transactions are complete when the next instruction runs. If the next instruction is not a memory instruction, it is allowed to run out of order. The DMB provides slightly looser memory barrier than DSB on ARM.

Definition at line 180 of file ARMCore.h.

◆ dsb()

void dsb ( )

inline

Data Synchronisation Barrier.

Enforces a strict memory barrier which ensures all memory transactions are completed when the next instruction begins. The DSB is the most strict memory barrier available on ARM.

See also: ARM1176JZF-S Technical Reference Manual, page 342, Data Synchronization Barrier

Definition at line 198 of file ARMCore.h.

◆ flushBranchPrediction()

void flushBranchPrediction ( )

inline

Flush branch prediction.

Definition at line 210 of file ARMCore.h.

Referenced by ARMCacheV6::cleanInvalidate(), and ARMCacheV7::cleanInvalidate().

◆ flushPrefetchBuffer()

void flushPrefetchBuffer ( )

inline

Flush Prefetch Buffer.

Definition at line 230 of file ARMCore.h.

Referenced by ARMCacheV6::cleanInvalidate(), and ARMControl::write().

◆ isb()

void isb ( )

inline

Instruction Synchronisation Barrier (ARMv7 and above)

Definition at line 218 of file ARMCore.h.

Referenced by ALIGN().

◆ tlb_flush_all()

void tlb_flush_all ( )

inline

Flush the entire Translation Lookaside Buffer.

Definition at line 161 of file ARMCore.h.

◆ trapKernel1()

ulong trapKernel1	(	ulong	api,
		ulong	arg1
	)

inline

Perform a kernel trap with 1 argument.

Parameters

api	Unique number of the handler to execute.
arg1	First argument

Returns: An integer.

Definition at line 59 of file ARMTraps.h.

Referenced by SystemInfo().

◆ trapKernel2()

ulong trapKernel2	(	ulong	api,
		ulong	arg1,
		ulong	arg2
	)

inline

Perform a kernel trap with 2 arguments.

Parameters

api	Unique number of the handler to execute.
arg1	First argument
arg2	Second argument

Returns: An integer

Definition at line 80 of file ARMTraps.h.

Referenced by PrivExec().

◆ trapKernel3()

ulong trapKernel3	(	ulong	api,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3
	)

inline

Perform a kernel trap with 3 arguments.

Parameters

api	Unique number of the handler to execute.
arg1	First argument
arg2	Second argument
arg3	Third argument

Returns: An integer.

Definition at line 103 of file ARMTraps.h.

Referenced by VMCtl(), and VMShare().

◆ trapKernel4()

ulong trapKernel4	(	ulong	api,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3,
		ulong	arg4
	)

inline

Perform a kernel trap with 4 arguments.

Parameters

api	Unique number of the handler to execute.
arg1	First argument
arg2	Second argument
arg3	Third argument
arg4	Fourth argument

Returns: An integer.

Definition at line 128 of file ARMTraps.h.

Referenced by ProcessCtl().

◆ trapKernel5()

ulong trapKernel5	(	ulong	api,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3,
		ulong	arg4,
		ulong	arg5
	)

inline

Perform a kernel trap with 5 arguments.

Parameters

api	Unique number of the handler to execute.
arg1	First argument
arg2	Second argument
arg3	Third argument
arg4	Fourth argument
arg5	Fifth argument

Returns: An integer.

Definition at line 156 of file ARMTraps.h.

Referenced by VMCopy().

Variable Documentation

◆ ALIGN

class ARMCore ALIGN

Namespaces

Data Structures

Macros

Functions

Variables

ARM Kernel Traps

Detailed Description

Macro Definition Documentation

◆ ABT_MODE

◆ ARM64_EX_VECTAB_SIZE

◆ ARM_EX_VECTAB_SIZE

◆ ASYNC_ABORT_BIT

◆ contain_flags

◆ cpu_reboot

◆ cpu_shutdown

◆ DIR_MASK

◆ DIRSHIFT

◆ ELR

◆ ERET

◆ FIQ_BIT

◆ FIQ_MODE

◆ GET_PT_TYPE

◆ HYP_MODE

◆ idle

◆ IRQ

◆ IRQ_BIT

◆ IRQ_MODE

◆ IS_PT_BLOCK

◆ IS_PT_PAGE_TBL

◆ L1_BLOCK_MASK

◆ L1_BLOCK_RANGE

◆ L1_BLOCK_SIZE

◆ L1_DIRSHIFT

◆ L1_IDX

◆ L2_BLOCK_MASK

◆ L2_BLOCK_RANGE

◆ L2_BLOCK_SIZE

◆ L2_DIRSHIFT

◆ L2_IDX

◆ L3_DIRSHIFT

◆ L3_IDX

◆ mcr

◆ mcrr

◆ MEMALIGN [1/2]

◆ MEMALIGN [2/2]

◆ MODE_MASK

◆ mrc

◆ mrrc

◆ PAGEDIR_MAX [1/2]

◆ PAGEDIR_MAX [2/2]

◆ PAGEDIR_SIZE [1/2]

◆ PAGEDIR_SIZE [2/2]

◆ PAGEMASK [1/2]

◆ PAGEMASK [2/2]

◆ PAGESHIFT

◆ PAGESIZE [1/2]

◆ PAGESIZE [2/2]

◆ PAGETAB_MAX [1/2]

◆ PAGETAB_MAX [2/2]

◆ PAGETAB_SIZE [1/2]

◆ PAGETAB_SIZE [2/2]

◆ PAGETAB_SPAN [1/2]

◆ PAGETAB_SPAN [2/2]

◆ PT_AF

◆ PT_BLOCK

◆ PT_DEV

◆ PT_ISH

◆ PT_KERNEL

◆ PT_MEM

◆ PT_NC

◆ PT_NONE

◆ PT_NX

◆ PT_OSH

◆ PT_PAGE

◆ PT_RO

◆ PT_RW

◆ PT_TYPE_MASK

◆ PT_USER

◆ read_core_id

◆ SECTIONMASK