IntelCore.h

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/*
 * Copyright (C) 2015 Niek Linnenbank
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
#ifndef __LIBARCH_INTEL_CPU_H
#define __LIBARCH_INTEL_CPU_H
 
#include <Types.h>
#include <Macros.h>
#include "IntelIO.h"
 
inline u64 timestamp()
{
    unsigned long long val;
    asm volatile ("rdtsc\n" : "=A"(val));
    return val;
}
 
#define cpu_reboot() \
({ \
    IntelIO io; \
    io.outb(0x64, 0xfe); \
})
 
#define cpu_shutdown() \
({ \
    IntelIO io; \
    io.outw(0xB004, 0x0 | 0x2000); \
})
 
#define idle() \
    asm volatile ("hlt");
 
#define ltr(sel) \
({ \
    u16 tr = sel; \
    asm volatile ("ltr %0\n" :: "r"(tr)); \
})
 
#define tlb_flush(addr) \
    asm volatile("invlpg (%0)" ::"r" (addr) : "memory")
 
#define tlb_flush_all() \
    asm volatile("mov %cr3, %eax\n" \
                 "mov %eax, %cr3\n")
 
#define INTEL_DIVZERO   0
#define INTEL_DEBUGEX   1
#define INTEL_NMI       2
#define INTEL_BREAKP    3
#define INTEL_OVERFLOW  4
#define INTEL_BOUNDS    5
#define INTEL_OPCODE    6
#define INTEL_DEVERR    7
#define INTEL_DOUBLEF   8
#define INTEL_COSEG     9
#define INTEL_TSSERR    10
#define INTEL_SEGERR    11
#define INTEL_STACKERR  12
#define INTEL_GENERR    13
#define INTEL_PAGEFAULT 14
#define INTEL_FLOATERR  16
#define INTEL_ALIGNERR  17
#define INTEL_MACHCHK   18
#define INTEL_SIMD      19
#define INTEL_VIRTERR   20
 
#define INTEL_EFLAGS_DEFAULT    (1 << 1)
#define INTEL_EFLAGS_IRQ        (1 << 9)
 
typedef struct TSS
{
    u32 backlink;
    u32 esp0, ss0;
    u32 esp1, ss1;
    u32 esp2, ss2;
    u32 cr3;
    u32 eip;
    u32 eflags;
    u32 eax,ecx,edx,ebx;
    u32 esp, ebp;
    u32 esi, edi;
    u32 es, cs, ss, ds, fs, gs;
    u32 ldt;
    u32 bitmap;
}
TSS;
 
typedef struct Segment
{
    u32 limitLow:16;
    u32 baseLow:16;
    u32 baseMid:8;
    u32 type:5;
    u32 privilege:2;
    u32 present:1;
    u32 limitHigh:4;
    u32 granularity:4;
    u32 baseHigh:8;
}
Segment;
 
typedef struct SegRegs
{
    /* Segments. */
    u32 gs, fs, es, ds, ss0;
}
SegRegs;
 
typedef struct CPURegs
{
    u32 edi, esi, ebp, esp0, ebx, edx, ecx, eax;
}
CPURegs;
 
typedef struct IRQRegs0
{
    u32 eip, cs, eflags;
}
IRQRegs0;
 
typedef struct IRQRegs3
{
    u32 eip, cs, eflags, esp3, ss3;
}
IRQRegs3;
 
typedef struct CPUState
{
    /* Segments. */
    SegRegs seg;
 
    /* By pusha */
    CPURegs regs;
 
    /* Vector/error arguments. */
    u32 vector, error;
 
    /* Pushed by processor. */
    IRQRegs3 irq;
}
CPUState;
 
class IntelCore
{
  public:
 
    void logException(CPUState *state) const;
 
    void logState(CPUState *state) const;
 
    void logRegister(const char *name, u32 reg) const;
 
    volatile u32 readCR2() const;
 
    volatile u32 readCR3() const;
 
    void writeCR3(u32 cr3) const;
};
 
#ifdef __KERNEL__
 
extern Segment gdt[];
 
extern TSS kernelTss;
 
extern Address kernelPageDir[];
 
#endif /* __KERNEL__ */
 
#endif /* __LIBARCH_INTEL_CPU_H */