FreeNOS
PL011.cpp
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1/*
2 * Copyright (C) 2015 Niek Linnenbank
3 * Copyright (C) 2013 Goswin von Brederlow <goswin-v-b@web.de>
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <FreeNOS/Constant.h>
20#include <FreeNOS/User.h>
21#include "PL011.h"
22
24{
25 return new PL011(UART0_IRQ);
26}
27
28PL011::PL011(const u32 irq)
29 : SerialDevice(irq)
30{
31 m_identifier << "serial0";
32}
33
35{
36 if (!isKernel)
37 {
38 // Remap IO base to ensure we have user-level access to the registers.
39 if (m_io.map(UART_BASE, PAGESIZE*2,
41 != IO::Success)
42 {
44 }
45
46 // Disable receiving interrupts
48 }
49 else
50 {
51 m_io.setBase(UART_BASE);
52 }
53
54 // Disable PL011.
55 m_io.write(PL011_CR, 0x00000000);
56
57 // Clear pending interrupts.
58 m_io.write(PL011_ICR, 0x7FF);
59
60 // Set integer & fractional part of baud rate.
63
64 // Disable FIFO, use 8 bit data transmission, 1 stop bit, no parity
66
67 if (isKernel)
68 {
69 // Mask all interrupts.
70 m_io.write(PL011_IMSC, (1 << 1) | (1 << 4) | (1 << 5) |
71 (1 << 6) | (1 << 7) | (1 << 8) |
72 (1 << 9) | (1 << 10));
73 }
74 else
75 {
76 // Enable Rx/Tx interrupts
79 }
80
81 // Enable PL011, receive & transfer part of UART.
82 m_io.write(PL011_CR, (1 << 0) | (1 << 8) | (1 << 9));
83
85}
86
88{
89 // Clear Receive Interrupts
90 u32 mis = m_io.read(PL011_MIS);
91 if (mis & PL011_MIS_RXMIS)
93
94 // Clear Transmit Interrupts
95 mis = m_io.read(PL011_MIS);
96 if (mis & PL011_MIS_TXMIS)
98
99 // Re-enable interrupts
100 if (!isKernel)
101 {
103 }
104
105 return FileSystem::Success;
106}
107
109 Size & size,
110 const Size offset)
111{
112 Size bytes = 0;
113
114 // Clear Receive Interrupts
115 u32 mis = m_io.read(PL011_MIS);
116 if (mis & PL011_MIS_RXMIS)
118
119 // Read as much bytes as possible
120 while (!(m_io.read(PL011_FR) & PL011_FR_RXFE) && bytes < size)
121 {
122 //buffer[bytes++] = m_io.read(PL011_DR);
123 u8 byte = m_io.read(PL011_DR);
124 buffer.bufferedWrite(&byte, 1);
125 bytes++;
126 }
127
128 if (buffer.getCount())
129 {
130 size = buffer.getCount();
131 return FileSystem::Success;
132 }
133 else
134 {
136 }
137}
138
140 Size & size,
141 const Size offset)
142{
143 Size bytes = 0;
144
145 // Clear Transmit Interrupts
146 u32 mis = m_io.read(PL011_MIS);
147 if (mis & PL011_MIS_TXMIS)
149
150 // Write as much bytes as possible
151 while (bytes < size)
152 {
154 {
155 m_io.write(PL011_DR, buffer[bytes++]);
156 }
157 }
158
159 if (bytes)
160 {
161 size = bytes;
162 return FileSystem::Success;
163 }
164 else
165 {
167 }
168}
void write(u32 reg, u32 data)
write to memory mapped I/O register
Definition ARMIO.h:46
u32 read(u32 reg) const
read from memory mapped I/O register
Definition ARMIO.h:62
static T * create()
Abstract function to create an instance of T.
String m_identifier
Unique identifier for this Device.
Definition Device.h:79
Abstract Input/Output buffer.
Definition IOBuffer.h:38
Size getCount() const
Get byte count.
Definition IOBuffer.cpp:109
FileSystem::Result bufferedWrite(const void *buffer, const Size size)
Buffered write bytes to the I/O buffer.
Definition IOBuffer.cpp:146
void setBase(const Address base)
Set memory I/O base offset.
Definition IO.cpp:33
Result map(Address phys, Size size=4096, Memory::Access access=Memory::Readable|Memory::Writable|Memory::User)
Map I/O address space.
Definition IO.cpp:38
@ Success
Definition IO.h:44
The PL011 is a commonly available UART device frequently found in ARM systems.
Definition PL011.h:40
PL011(const u32 irq)
Constructor.
Definition PL011.cpp:28
virtual FileSystem::Result write(IOBuffer &buffer, Size &size, const Size offset)
Write bytes to the device.
Definition PL011.cpp:139
virtual FileSystem::Result interrupt(const Size vector)
Called when an interrupt has been triggered for this device.
Definition PL011.cpp:87
virtual FileSystem::Result initialize()
Initializes the UART.
Definition PL011.cpp:34
@ PL011_FR
Definition PL011.h:50
@ PL011_IMSC
Definition PL011.h:64
@ PL011_MIS
Definition PL011.h:70
@ PL011_ICR_TXIC
Definition PL011.h:75
@ PL011_FR_RXFE
Definition PL011.h:51
@ PL011_MIS_TXMIS
Definition PL011.h:72
@ PL011_FBRD
Definition PL011.h:56
@ PL011_LCRH_WLEN_8BIT
Definition PL011.h:59
@ PL011_LCRH
Definition PL011.h:58
@ PL011_MIS_RXMIS
Definition PL011.h:71
@ PL011_ICR_RXIC
Definition PL011.h:76
@ PL011_DR
Definition PL011.h:47
@ PL011_ICR
Definition PL011.h:74
@ PL011_IBRD
Definition PL011.h:55
@ PL011_CR
Definition PL011.h:61
@ PL011_FR_TXFE
Definition PL011.h:52
@ PL011_IMSC_RXIM
Definition PL011.h:65
virtual FileSystem::Result read(IOBuffer &buffer, Size &size, const Size offset)
Read bytes from the device.
Definition PL011.cpp:108
Provides sequential byte stream of incoming (RX) and outgoing (TX) data.
const u32 m_irq
interrupt vector
Arch::IO m_io
I/O instance.
#define SELF
Definition ProcessID.h:35
API::Result ProcessCtl(const ProcessID proc, const ProcessOperation op, const Address addr=0, const Address output=0)
Prototype for user applications.
Definition ProcessCtl.h:93
@ DisableIRQ
Definition ProcessCtl.h:45
@ EnableIRQ
Definition ProcessCtl.h:44
#define PAGESIZE
ARM uses 4K pages.
Definition ARMConstant.h:97
C uint isKernel
Non-zero if this executable is linked as the kernel.
unsigned int u32
Unsigned 32-bit number.
Definition Types.h:53
unsigned int Size
Any sane size indicator cannot go negative.
Definition Types.h:128
unsigned char u8
Unsigned 8-bit number.
Definition Types.h:59
Result
Result code for filesystem Actions.
Definition FileSystem.h:53
@ User
Definition Memory.h:44
@ Readable
Definition Memory.h:41
@ Device
Definition Memory.h:48
@ Writable
Definition Memory.h:42